1. Field of the Invention
The present invention relates to a method of fabricating semiconductor devices, and more particularly, to a method of forming a contact structure of a semiconductor device.
2. Description of the Related Art
With the increase in the integration level or density of semiconductor devices, MOS transistors have become smaller, and the aspect ratios of a contact holes, i.e., the ratio of the lengths of the holes to their widths, increase. When the size (channel length) of a MOS transistor deceases, a short channel effect results such that the electrical characteristics of MOS transistors are degraded. Thus, an impurity layer, such as the source/drain region of a MOS transistor, which is used in highly-integrated semiconductor devices, must be formed to be very thin. However, when the junction depth of an impurity layer is thinly formed, a junction spiking phenomenon occurs in which metal atoms within a metal interconnection, which contacts the impurity layer via a contact hole, penetrate into a semiconductor substrate below the impurity layer.
Accordingly, recent techniques for solving the junction spiking problem by interposing a barrier metal layer and an ohmic metal layer between a metal interconnection and an impurity layer are being prevalently used for highly-integrated semiconductor devices. Also, the barrier metal layer and the ohmic metal layer are being widely used to form a multi-layered metal interconnection. That is, a technique of interposing an ohmic metal layer and a barrier metal layer between a lower metal interconnection exposed by a via hole and an upper metal interconnection which contacts the lower metal interconnection, is being prevalently used.
Also, to increase the integration level of a semiconductor device, the size of a pattern formed in a predetermined region of a semiconductor device, for example, the width of a pattern which defines an impurity layer which is formed in the cell array region or the core region of the semiconductor device, must be as narrow as the width of a pattern depending on the minimum design rule. At this time, when a contact hole is formed on the impurity layer, the bottom area of the contact hole is limited within the width of the impurity layer, thus making it difficult to improve contact resistance. Hence, a process for maximizing the surface area of an impurity layer that is exposed by a contact hole, by forming the contact hole for exposing the impurity layer and also part of an isolation region adjacent to the impurity layer, is being developed.
FIG. 1 is a layout diagram of a metal contact structure which is commonly used in the present invention and in the prior art. Here, a region indicated by reference character a denotes a region in which a first active region 1a and a first metal contact hole 3a for exposing both the first active region 1a and a part of the isolation regions adjacent to the first active region 1a are laid out. A region indicated by reference character b denotes a region in which a second active region 1b and a second metal contact hole 3b for exposing part of the second active region 1b are laid out.
FIGS. 2 through 4 are cross-sectional views, taken along line AAxe2x80x2 of FIG. 1, for illustrating a conventional method of forming a metal contact structure. Here, a portion indicated by reference character a denotes a portion in which the first metal contact hole 3a of FIG. 1 is formed, and a portion indicated by reference character b denotes a portion in which the second metal contact hole 3b of FIG. 1 is formed.
Referring to FIG. 2, an isolation layer 13 for defining an active region is formed on a predetermined region of the semiconductor substrate 11. The isolation layer 13 is formed by forming a trench through etching of the predetermined region of the semiconductor substrate 11 and filling the trench with an insulating layer such as a silicon oxide layer. First and second impurity layers 15a and 15b are formed by implanting impurities having a different conductivity type than the conductivity type of the semiconductor substrate 11, such as N-type or P-type impurities, into the surface of the active region between adjacent isolation layers 13. The first impurity layer 15a is narrower than the second impurity layer 15b. An inter;-dielectric layer 17 is formed on the entire surface of the semiconductor substrate 11 on which the first and second impurity layers 15a and 15b have been formed.
Referring to FIG. 3, first and second metal contact holes H1 and H2 for exposing the first and second impurity layers 15a and 15b, respectively, are formed by patterning the inter-dielectric layer 17. The first metal contact hole H1 is formed so that a portion of the isolation layer 13 adjacent to the first impurity layer 15a is exposed, in order to maximize the area of the first impurity layer 15a that is exposed. At this time, the isolation layer 13 is also etched, resulting in a recessed region which exposes the sidewalls of the first impurity layer 15a. When over-etching is performed to pattern the first and second metal contact holes H1 and H2, recessed regions, which expose the sidewalls of the first impurity layer 15a and also the semiconductor substrate 11 portion below the first impurity layer 15a, may be formed.
Next, an ohmic metal layer 19 and a barrier metal layer 21 are sequentially formed on the entire surface of the semiconductor substrate on which the first and second metal contact holes H1 and H2 have been formed. The ohmic metal layer 19 and the barrier metal layer 21 are formed of titanium and titanium nitride, respectively. A sputtering process is generally used to form the ohmic metal layer 19 and the barrier metal layer 21. The ohmic metal layer 19 portion and the barrier metal layer 21 portion deposited on the bottoms and sidewalls of the first and second metal contact holes H1 and H2, respectively, are thinner than those deposited on the upper surface of the inter-dielectric layer 17, due to the characteristics of the sputtering process. In particular, as the aspect ratios of the first and second metal contact holes H1 and H2 increase, the step coverages of the ohmic metal layer 19 and the barrier metal layer 21 formed by the sputtering process become poor. Thus, when the ohmic metal layer 19 and the barrier metal layer 21 are formed after a metal contact hole having a high aspect ratio is formed, the ohmic metal layer 19 portion and the barrier metal layer 21 portion at the lower corners C1 and C2 of the first and second metal contact holes H1 and H2 are very thin, as shown in FIG. 3. The ohmic metal layer 19 portions at the lower corners C1 of the first metal contact hole H1 contact the sidewalls of the first impurity layer 15a, and also may directly contact the semiconductor substrate 11.
Referring to FIG. 4, the resultant structure on which the ohmic metal layer 19 and the barrier metal layer 21 have been formed is thermally treated to react the ohmic metal layer 19 with the impurity layers 15a and 15b. Thus, first and second metal silicide Layers 19a and 19b are formed on the first and second impurity layers 15a and 15b, respectively. Here, the edges of the first metal silicide layer 19a formed on the first impurity layer 15a can make contact with the semiconductor substrate 11 as shown in FIG. 4. Consequently, when a reverse bias is applied between the first impurity layer 15a and the semiconductor substrate 11, the amount of junction leakage current significantly increases on account of the first metal silicide layer 19a, causing malfunction of the device.
Next, a metal layer 23 for filling the first and second contact holes H1 and H2, for example, a tungsten layer, is formed on the entire surface of the semiconductor substrate on which the first and second metal silicide layers 19a and 19b have been formed. The metal layer 23, that is, the tungsten layer, for forming a contact plug, is formed by low pressure chemical vapor deposition (LPCVD) in which WF6 gas is used as a source gas. At this time, fluorine (F) decomposed from the WF6 gas passes through portions of the barrier metal layer 21 at the lower corners C1 and C2 of the first and second metal contact holes H1 and H2, particularly, at the lower corner C2 of the second metal contact hole H2, and reacts with portions of the ohmic metal layer 19 at the edges of the second metal silicide layer 19b. Thus, metal fluoride layers I, for example, titanium fluoride layers TiF, are formed on the upper surfaces of the edge portions of the second metal silicide layer 19b. The metal fluoride layer I is insulating, so that it is a factor in increasing the contact resistance of the second metal contact hole. This increase in the contact resistance becomes more serious with a reduction in the size (i.e., the diameter) of a metal contact hole.
FIGS. 5 and 6 are cross-sectional views illustrating another conventional method of forming a metal contact structure. Here, the same reference numerals as those used in FIGS. 2 through 4 denote the same items. In the method of forming a metal contact structure illustrated by FIGS. 5 and 6, a lower portion below the contact hole is not an impurity layer as shown in FIGS. 2 through 4, but a conductive layer pattern which includes metal.
Referring to FIG. 5, an insulative layer 17 is formed on a semiconductor substrate 11, and a lower interconnection 31, which is a metal polycide pattern containing a refractory metal or a doped polysilicon pattern, is formed on a predetermined area of the insulative layer 17. An inter-dielectric layer 33 is formed on the entire surface of the semiconductor substrate on which the lower interconnection 31 has been formed. The inter-dielectric layer 33 is patterned to form a metal contact hole which exposes a predetermined area of the lower interconnection 31. An ohmic metal layer 19xe2x80x2 and a barrier metal layer 21xe2x80x2 are sequentially formed on the entire surface of the semiconductor substrate on which the metal contact hole has been formed. Here, the ohmic metal layer 19xe2x80x2 and the barrier metal layer 21xe2x80x2 are formed by the same method as the method of forming the ohmic metal layer 19 and the barrier metal layer 21, which is described above referring to FIG. 3. Therefore, portions of the ohmic metal layer 19xe2x80x2 and the barrier metal layer 21xe2x80x2 at the lower corners of the metal contact hole are very thin.
Referring to FIG. 6, a metal layer 23xe2x80x2 for filling the metal contact hole, for example, a tungsten layer, is formed on the entire surface of the semiconductor substrate on which the ohmic metal layer 19xe2x80x2 and the barrier metal layer 21xe2x80x2 have been formed. The metal layer 23xe2x80x2, that is, a tungsten layer, for forming a contact plug within the metal contact hole, is formed by LPCVD in which WF6 gas is used as a source gas. At this time, fluorine (F) decomposed from the WF6 gas passes through portions of the ohmic metal layer 19xe2x80x2 and the barrier metal layer 21xe2x80x2 formed thinly at the lower corners of the metal contact hole, and penetrate into the lower interconnection 31. Thus, when the lower interconnection 31 is a metal polycide pattern, the fluorine F reacts with metal atoms within the metal polycide pattern. Consequently, portions of the lower interconnection below the corners of the metal contact hole are consumed, resulting in voids V. The formation of the voids V below the corners of the metal contact hole reduces the area of contact between the ohmic metal layer 19xe2x80x2 and the lower interconnection 31, thus increasing the contact resistance.
When the lower interconnection 31 is a doped polysilicon pattern, fluorine (F) decomposed from the WF6 gas reacts with the ohmic metal layer 19xe2x80x2 formed thinly at the lower corners of the metal contact hole as described referring to FIG. 4, that is, with a titanium layer. Consequently, a metal fluoride layer is formed at the lower corners of the metal contact hole, thus increasing the contact resistance.
According to these conventional methods of forming contact structures as described above, the junction leakage current characteristics of an impurity layer are deteriorated, and a contact resistance increases. In particular, increases in the contact resistance are due to the poor step coverages of an ohmic metal layer and a barrier metal layer. In response to this problem, a sputtering process using collimators has been proposed to form an ohmic metal layer and a barrier metal layer, with both having an excellent step coverage within a contact hole. However, this sputtering process is eventually unsatisfactory to improve the step coverages of the ohmic metal layer and the barrier metal layer which are formed within a contact hole having a high aspect ratio. Alternatively, a chemical vapor deposition (CVD) method providing an excellent step coverage can be used to form an ohmic metal layer and a barrier metal layer, for example, a titanium layer and a titanium nitride layer. However, the CVD method has a problem in that chlorine decomposed from TiCl4 gas used as a source gas, corrodes a lower interconnection containing metal. Therefore, a method capable of improving the contact resistance and junction leakage current characteristics of highly-integrated semiconductor devices including a contact hole having a high aspect ratio is required.
An object of the present invention is to provide a method of forming a contact structure of a semiconductor device by which a contact resistance and junction leakage current characteristics can be enhanced.
In accordance with the invention, there is provided a method of forming a contact structure of a semiconductor device. In accordance with the method of the invention, an inter-dielectric layer is formed on a semiconductor substrate in which a lower interconnection is formed. A contact hole is formed, which exposes a predetermined region of the lower interconnection, by patterning the inter-dielectric layer. A conformal semiconductor layer is formed along the profile of the contact hole on the entire surface of the semiconductor substrate on which the contact hole has been formed. An ohmic layer is formed on the conformal semiconductor layer, and a compound material layer is formed by reacting the conformal semiconductor layer with the ohmic metal layer by thermally treating the ohmic metal layer. An unreacted ohmic metal layer, which did not react with the conformal semiconductor layer, is removed, and a barrier metal layer is formed on the entire surface of the resulting structure.
In one embodiment, the method further includes formation of a contact plug within the contact hole of the thermally-processed semiconductor substrate and formation of a metal interconnection on the contact plug. The contact plug can be a refractory metal layer such as a tungsten layer, and the metal interconnection can be a metal layer such as an aluminum layer or aluminum alloy layer.
Specifically, the method can include forming a refractory metal layer for filling the contact hole on the entire surface of the semiconductor substrate on which the barrier metal layer has been formed. The refractory metal layer, the barrier metal layer and the compound material layer can be planarized until the upper surface of the inter-dielectric layer is exposed, thereby forming a compound material liner and a barrier metal liner on the bottom and sidewalls of the contact hole and simultaneously forming a contact plug for filling the region surrounded by the barrier metal liner. A metal interconnection can then be formed on the contact plug. In one embodiment, the refractory metal layer is formed of tungsten.
A predetermined region of the semiconductor substrate which is exposed by the contact hole is a lower interconnection. The lower interconnection can be an impurity layer obtained by implanting impurities having a different conductivity type than the conductivity type of the semiconductor substrate. These impurities are implanted into an active region defined by an isolation layer. Also, the lower interconnection can be a metal polycide pattern or a doped polysilicon pattern.
When the lower interconnection is an impurity layer, the contact hole may expose an impurity layer and portions of the isolation layer adjacent to the impurity layer together, or expose only a predetermined region of the impurity layer.
In one embodiment, the conformal semiconductor layer can be formed of a material selected from the group consisting of undoped silicon (Si), undoped germanium (Ge) and undoped silicon germanium (SiGe). In one embodiment, the ohmic metal layer and the barrier metal layer are formed of titanium and titanium nitride, respectively. In one embodiment, the semiconductor layer is formed by chemical vapor deposition (CVD) which provides an excellent step coverage.
Rapid thermal processing (RTP) can be performed to react the semiconductor layer with the ohmic metal layer, at 600 to 700xc2x0 C. under a nitrogen, atmosphere.
In another aspect, the invention is directed to another method of forming a contact structure of a semiconductor device. An isolation layer for defining an active region is formed on a predetermined area of a semiconductor substrate. An impurity layer informed by implanting impurities having a different conductivity type than the conductivity type of the semiconductor substrate onto the surface of the active region. An inter-diaelectric layer is formed on the entire surface of the semiconductor substrate on which the impurity layer has been formed. A metal contact hole, which exposes a predetermined region of the impurity layer and has a recessed region, the recessed region being an etched portion of the isolation layer adjacent exposed impurity layer, is formed by patterning the inter-diaelectric layer. A silicon layer residue, which contacts the sidewalls of the exposed impurity layer, is formed within the recessed region. A metal silicide liner is formed to cover the sidewalls of the metal contact hole, the surface of the exposed impurity layer, and the silicon layer residue. A barrier metal liner is formed on the metal silicide liner. A contact plug is formed for filling the region surrounded by the barrier metal liner.
In one embodiment, the isolation layer is formed by trench isolation.
In one embodiment, the steps of forming the silicon layer residue, the metal silicide liner, the barrier metal liner and the contact plug include sequentially forming a silicon layer and an ohmic metal layer on the entire surface of the semiconductor substrate on which the metal contact hole has been formed. A metal silicide layer is formed by thermally processing the ohmic metal layer to cause the ohmic layer to react with the silicon layer. The silicon layer residue, which contacts the sidewalls of the exposed impurity layer within the recessed region, is simultaneously formed. A barrier metal layer is formed on the entire surface of the semiconductor substrate on which the metal silicide layer and the silicon layer residue have been formed. A refractory metal layer for filling the metal contact hole is formed on the entire surface of the semiconductor substrate on which the barrier metal layer has been formed. The refractory metal layer, the barrier metal layer, and the metal silicide layer are sequentially planarized until the upper surface of the inter-diaelectric layer is exposed. In one embodiment, after the metal silicide layer is formed, a portion of the ohmic metal layer which does not react with the silicon layer upon thermal treatment is removed.
In one embodiment, the silicon layer residue is an undoped polycrystalline silicon layer or an undoped amorphous silicon layer. In one embodiment, the ohmic metal layer and the barrier metal layer are a titanium layer and a titanium nitride layer, respectively.
A metal interconnection can be formed on the contact plug. The contact plug can be a tungsten layer.
In another aspect, the invention is directed to another method of forming a contact structure of a semiconductor device. An isolation layer for defining an active region is formed on a predetermined area of a semiconductor substrate. An impurity layer is formed by implanting impurities having a different conductivity type than the conductivity type of the semiconductor substrate onto the surface of the active region. An inter-diaelectric layer is formed on the entire surface of the semiconductor substrate on which the impurity layer has been formed. A metal contact hole, which exposes a predetermined region of the impurity layer and has a recessed region, the recessed region being an etched portion of the isolation layer adjacent to the exposed impurity layer, is formed by patterning the inter-diaelectric layer. A conformal silicon layer is formed along a profile of the metal contact hole on the entire surface of the semiconductor substrate on which the metal contact hole has been formed. An ohmic metal layer and a barrier metal layer are formed on the silicon layer. The semiconductor substrate on which the barrier metal layer has been formed is thermally processed to form a metal silicide layer obtained by reacting the ohmic metal layer with the silicon layer and simultaneously forming silicon layer residues within the recessed region. A contact plug is formed for filling the metal contact hole surrounded by the barrier metal layer.
In one embodiment, the isolation layer is formed by trench isolation. In one embodiment, the silicon layer is an undoped polycrystalline layer or an undoped amorphous silicon layer. In one embodiment, the ohmic metal layer and the barrier metal layer are a titanium layer and a titanium nitride layer, respectively. A metal interconnection can be formed on the contact plug. The contact plug can be a tungsten layer.
According to the present invention as described above, after a contact hole is formed, a semiconductor layer having an excellent step coverage is interposed between an ohmic metal layer and a portion of a lower interconnection which is exposed by the contact hole. Accordingly, a compound material layer having a uniform thickness, for example, a metal silicide layer, is formed on the sidewalls and bottom of the contact hole upon thermal processing. When the semiconductor layer and the ohmic metal layer are an undoped silicon layer and a titanium layer, respectively, the compound material layer is a titanium silicide layer. The compound material layer can prevent atoms such as fluorine decomposed from WF6 gas which is used as a source gas, from penetrating into the lower interconnection while a refractory metal layer for forming a contact plug, that is, a tungsten layer, is formed within the contact hole. Therefore, increases in contact resistance can be prevented.
Also, when a contact hole for exposing an impurity layer and portions of an isolation layer adjacent to the impurity layer is formed, this can prevent a compound material layer (i.e., a metal silicide layer)formed on the surface of the impurity layer from directly contacting the semiconductor substrate by the silicon layer residue formed within the recessed region. Hence, the characteristics of junction leakage current flowing between the impurity layer and the semiconductor substrate can be improved.